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| iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 1/26 FEATURES E E E E E E E E E E E E Bidirectional BiSS sensor communication with up to 3 slaves Supports SSI protocol for unidirectional communication Synchronous sensor data acquisition with cyclic transfer at data rates of up to 10 Mbit/s Command and slave register operations during cyclic data transfers Data lengths of up to 64 bits for sensor data, independently scalable for each slave Automatic compensation of line delays, measurement and conversion times Data verification by CRC polynomials of up to 8 bits, adjustable per slave Separate memory banks enable free controller access during BiSS sensor data transfers 32 bytes of intermediate memory to ease bidirectional slave register communications Parallel controller interface with an 8-bit data/address bus services Intel and Motorola devices Serial controller communication by SPITM-compatible mode Single 3 to 5V supply, industrial temperature range APPLICATIONS E E E Bidirectional device communication in multisensor systems Position measurement with linear or angular encoders Drive systems (motor feedback) PACKAGES TSSOP24 BLOCK DIAGRAM SPI is a trademark of MOTOROLA, Inc. Copyright (c) 2003, 2009, iC-Haus www.ichaus.com iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 2/26 DESCRIPTION iC-MB3 is a single-chip BiSS/SSI interface controller featuring an 8-bit bus interface to industrial standard microcontrollers. An additional SPI interface mode also enables serial communication between iC-MB3 and the connected microcontroller. One to three BiSS devices can be attached to the sensor side of the device. These are connected up to clock line MA1 and data return line SL1 using RS422 transceivers (Figure 1). The BiSS devices can be connected directly in noise-free environments. A maximum of three BiSS slaves is supported, each with their own independently scalable data sections encompassing: 1) Sensor data from 0 to 64 bits (for measurement data, alarms and warnings) 2) Register data with 128 bytes per slave ID (e.g. for device parameters). iC-MB3 provides dual RAM memory banks for each slave, enabling flexible access of the microcontroller while new sensor data is being read in. A 32-byte intermediate memory supports register transfers. Sensor data acquisition is started by a microcontroller command or via pin GETSENS. Alternatively, iC-MB3 can also read in new sensor data automatically; the cycle time in this instance can be set as required. The end of sensor data acquisition and readin is signaled at pin EOT by a high; if faults occur during transmission pin NER signals a low. Errors in communication can be verified by the microcontroller via a status register; a system error message can also enter this register if bidirectional message pin NER is kept low by external intervention. iC-MB3 generates a clock signal for sensor communication using an internal 20 MHz oscillator. The clock can also be supplied externally. Figure 1: Point-to-point connection of iCFigure 2: Example network of iC-MB3 and three subscribers. All MB3 and one bus subscriber. This can use 1 8 possible slave IDs (SIDs) are used distributed. to 8 slave IDs (SID). iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 3/26 PACKAGES TSSOP24 to JEDEC Standard PIN CONFIGURATION TSSOP24 4.4 mm, lead pitch 0.65 mm (top view) PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NCS ALE-SCLK DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND VDD EOT GETSENS NER MA1 SL1 INT_NMOT CFGSPI Chip Select Input, low active Address Latch Enable Input Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Ground +3.3 ... +5V Supply Voltage End-Of-Transmission Output Sensor Data Request Input Error Message Input/Output, low active BiSS Clock/Data Line Output BiSS Data Line Input Mode Select (Intel = 1, Motorola = 0)* Serial/Parallel Mode Select Input (serial SPI = 1, parallel = 0) NRES Reset Input, low active CLK External Clock Input CLKOUT** Clock Output NWR_E Write Input, low active (Intel) Enable Input, high active (Motorola) NRD_RNW Read Input, low active (Intel) Read/Not-Write Select Input (Motorola) Serial SPI Communication Mode (CFGSPI = 1): 1 NCS Chip Select Input, low active 2 SCLK SPI Clock Input 3 SI SPI Serial Data Input 4 SO SPI Serial Data Output * only when CLKENI = 1 else no signal ** on SPI no effect iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 4/26 ABSOLUTE MAXIMUM RATINGS Values beyond which damage may occur; device operation is not guaranteed. Item Symbol Parameter Supply Voltage VDD Current in VDD Voltage at all pins, excluding VDD and GND Current in all pins excluding VDD and GND ESD Susceptibility at all pins Operating Junction Temperature Storage Temperature Range HBM, 100 pF discharged through 1.5 kS -40 -40 V()# VDD + 0.3 V Conditions Fig. Min. G001 VDD G002 I(VDD) G003 V() G004 I() E001 Vesd() TG1 Tj TG2 Ts -0.3 -20 -0.3 -10 Max. 6 30 6 10 2 150 150 V mA V mA kV C C Unit THERMAL DATA Operating Conditions: VDD = 3 ... 5 V Item T1 Symbol Ta Parameter Operating Ambient Temperature Range (extended range to -40 C is available on request) Conditions Fig. Min. -25 Typ. Max. 85 C Unit All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 5/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 3 ... 5.5 V, Tj = -25 ... +125 C, unless otherwise noted Item Symbol Parameter Conditions Tj C Total Device 001 VDD 002 I(VDD) 003 Vc()hi 004 Vc()lo Permissible Supply Voltage Supply Current in VDD Clamp Voltage hi at all pins excluding VDD, GND Clamp Voltage lo at all pins excluding VDD, GND outputs not loaded, f(CLK) = 20 MHz Vc()hi = V() - VDD, I() = 1 mA; outputs tristate I() = -1mA; outputs tristate 0.3 -1.6 3 5.5 20 1.6 -0.3 V mA V V Fig. Min. Typ. Max. Unit Control Interface: EOT, NER, GETSENS 201 Vs()hi Saturation Voltage hi at EOT Saturation Voltage lo at EOT, NER Threshold Voltage hi at NER, GETSENS Threshold Voltage lo at NER, GETSENS Threshold Voltage Hysteresis at NER, GETSENS Pull-Up Current at NER vs. VDD V() = 0 ... VDD - 1.5 V VDD = 3 V 0.8 0.4 300 -600 4 500 -300 35 -60 70 Vs()hi = VDD - V(); I() = -4 mA VDD = 3 V; I() = -2 mA I() = 4 mA VDD = 3 V, I() = 2 mA 400 400 420 420 2 mV mV mV mV V V V mV A A 202 Vs()lo 203 Vt()hi 204 Vt()lo 205 Vt()hys 206 Ipu() 207 Ipd() Pull-Down Current at GETSENS V() = 1.5 V ... VDD vs. GND Vs()hi = VDD - V(); I() = -4 mA VDD = 3 V, I() = -2 mA I() = 4 mA VDD = 3 V, I() = 2 mA BiSS Interface: MA1, SL1 301 Vs(MA1)hi Saturation Voltage hi 400 400 420 420 2 VDD = 3 V 305 Vt(SL1)hys Threshold Voltage Hysteresis 306 Ipu(SL1) Pull-Up Strom vs. VDD V() = 0 ... VDD - 1.5 V C Interface: bidirectional data bus DB7 ... 0, Inputs NWR_E, NRD_RNW, NCS, ALE, INT_NMOT, CFGSPI 401 Vs()hi Saturation Voltage hi at DB7...0 Saturation Voltage lo at DB7...0 Threshold Voltage hi Threshold Voltage lo VDD = 3 V 405 Vt()hys 406 Ipd() Threshold Voltage Hysteresis Pull-Down Current at DB7...0, ALE, CFGSPI, INT_NMOT to GND Pull-Up Current at NRD_RNW, NWR_E, NCS vs.VDD V() = 1.5 V ... VDD 0.8 0.4 300 4 500 35 70 Vs()hi = VDD - V(); I() = -4 mA VDD = 3 V, I() = -2 mA I() = 4 mA VDD = 3 V, I() = 2 mA 400 400 420 420 2 mV mV mV mV V V V mV A 0.8 0.4 300 -70 500 -35 -5 mV mV mV mV V V V mV A 302 Vs(MA1)lo Saturation Voltage lo 303 Vt(SL1)hi 304 Vt(SL1)lo Threshold Voltage hi Threshold Voltage lo 402 Vs()lo 403 Vt()hi 404 Vt()lo 407 Ipu() V() = 0 ... VDD - 1.5 V -70 -35 -4 A iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 6/26 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 3 ... 5.5 V, Tj = -25 ... +125 C, unless otherwise noted Item Symbol Parameter Conditions Tj C Oscillator: CLK, CLKOUT 501 f(CLK) Permissible Clock Rate at CLK VDD = 5 V, CLKENI = 1 0.8 0.4 300 V() = 1.5 V ... VDD 4 500 35 70 400 400 420 420 -30 5 -12 23 -4 50 20 20 2 VDD = 3 V 505 Vt(CLK)hys Threshold Voltage Hysteresis 506 Ipd() 507 Vs()hi Pull-Down Current at CLK Saturation Voltage hi at CLKOUT Vs()hi = VDD- V(); I()= -4 mA VDD = 3 V, I() = -2 mA Saturation Voltage lo at CLKOUT I() = 4 mA VDD = 3 V, I() = 2 mA Short-Circuit Current hi at CLKOUT Short-Circuit Current lo at CLKOUT Undervoltage Reset Undervoltage Release Undervoltage Hysteresis Threshold Voltage hi Threshold Voltage lo VDD = 3 V 606 Vt()hys 607 Ipd() 608 td()res Threshold Voltage Hysteresis Pull-Down Current Required Reset Pulse Duration at NRES V() = 1.5 V ... VDD 0.8 0.4 300 4 250 500 35 70 V() = 0 V() = VDD 25 MHz MHz V V V mV A mV mV mV mV mA mA 502 f(CLKOUT) Oscillator Clock Frequency 503 Vt(CLK)hi Threshold Voltage hi 504 Vt(CLK)lo Threshold Voltage lo Fig. Min. Typ. Max. Unit 508 Vs()lo 509 Isc()hi 510 Isc()lo Reset: NRES 601 VDDoff 602 VDDon 603 VDDhys 604 Vt()hi 605 Vt()lo VDD decreasing VDD increasing VDDhys = VDDon - VDDoff 1.6 1.75 100 2 V V mV V V V mV A ns iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 7/26 OPERATING REQUIREMENTS: C Interface, INTEL mode Operating conditions: CFGSPI = 0, INT_NMOT = 1 VDD = 3 ... 5.5V, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item I01 I02 I03 l04 l05 l06 l07 l08 l09 l10 l11 l12 l13 l14 Symbol tsAA tAh tsCA thAA tsAW tWl tsDW thWD thWC thWA thRA tsAR tRl tpRD1 tpRD2 Parameter Setup Time: Address stable before ALE hi6lo Signal Duration: ALE at high level Setup Time: NCS hi6lo until ALE hi6lo Hold Time: Address stable after ALE hi6lo Setup Time: ALE hi6lo until NWR_E hi6lo Signal Duration: NWR_E at low level Setup Time: Data stable before NWR_E lo6hi Hold Time: Data stable after NWR_E lo6hi Hold Time: NCS lo after NWR_E lo6hi Hold Time: ALE lo after NWR_E lo6hi Setup Time: ALE hi6lo until NRD_RNW hi6lo Signal Duration: NRD_RNW at low level Propagation Delay: Data stable after NRD_RNW hi6lo Propagation Delay: Data Bus high impedance after NRD_RNW lo6hi NCS = lo Conditions Fig. Min. 3/4 3/4 3/4 3/4 3 3 3 3 3 3/4 4 4 4 4 15 10 10 15 0 10 15 0 0 15 0 70 0 0 25 25 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Figure 3: Write cycle (Intel Mode) Figure 4: Read cycle (Intel Mode) iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 8/26 OPERATING REQUIREMENTS: C Interface, MOTOROLA mode Operating conditions: CFGSPI = 0, INT_NMOT = 0 VDD = 3 ... 5.5V, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item I20 I21 I22 l23 l24 l25 l26 l27 l28 l29 l30 l31 l32 Symbol tsAA tAh tsCA thAA tsAE tsRE tEh tsDE thED thEC thER tpED1 tpED2 Parameter Setup Time: Address stable before ALE hi6lo Signal Duration: ALE at high level Setup Time: NCS hi6lo until ALE hi6lo Hold Time: Address stable after ALE hi6lo Setup Time: ALE hi6lo until NWR_E lo6hi Setup Time: NRD_RNW lo6hi until NWR_E lo6hi Signal Duration: NWR_E at high level Setup Time: Data stable before NWR_E hi6lo Hold Time: Data stable before NWR_E hi6lo Hold Time: NCS lo after NWR_E hi6lo Hold Time: NRD_RNW lo after NWR_E hi6lo Propagation Delay: Data stable after NWR_E lo6hi Propagation Delay: Data bus high impedance after NWR_E hi6lo Hold Time: NWR_E hi6lo before ALE lo6hi NCS = lo Conditions Fig. Min. 5/6 5/6 5/6 5/6 5/6 5/6 5/6 5 5 5/6 5/6 6 6 15 10 10 15 0 0 10 15 0 0 0 0 0 25 25 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit l33 thEA 5/6 0 ns Figure 5: Write cycle (Motorola Mode) Figure 6: Read cycle (Motorola Mode) iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 9/26 OPERATING REQUIREMENTS: C Interface, SPI mode Operating conditions: CFGSPI = 1 VDD = 3 ... 5.5V, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item l40 l41 l42 l43 l44 l45 l46 l47 l48 Symbol tsCCL tsDCL thDCL tCLh tCLl thCLC tCSh tpCLD tpCSD Parameter Setup Time: NCS hi6lo until SCLK/ALE lo6hi Setup Time: SI/DB0 stable before SCLK/ALE lo6hi Hold Time: SI/DB0 stable after SCLK/ALE lo6hi Signal Duration SCLK/ALE hi Signal Duration SCLK/ALE lo Hold Time: NCS lo after SCLK/ALE lo6hi Signal Duration NCS hi Propagation Delay: SO/DB1 stable after SCLK/ALE hi6lo Propagation Delay: SO/DB1 high impedance after NCS lo6hi Conditions Fig. Min. 0.29 0.29 0.29 7a/b 7a/b 7a/b 7a/b 7b 7b 10 15 0 10 10 0 0 0 0 25 25 Max. ns ns ns ns ns ns ns ns ns Unit Figure 7: C interface in SPI mode with write cycle (top) and read cycles (bottom). iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 10/26 OPERATING REQUIREMENTS: BiSS Interface Operating conditions: Register bit SELSSI = 0 VDD = 3 ... 5.5 V, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item Symbol Parameter Conditions Fig. Min. Sensor Mode l60 l61 l62 l63 l64 TMAS tMASl tMASh tpLine tpL Clock Period Clock Signal Lo Level Duration Clock Signal Hi Level Duration Permissible Line Delay Permissible Propagation Delay of Subsequent Clock Cycles vs. 1st Clock Cycle Permissible Timeout (Slave) Clock Period "Logic 0" Hi Level Duration "Logic 1" Hi Level Duration Clock Signal Hi Level Duration Setup Time: SL1 stable before MA1 lo6hi Hold Time: SL1 stable before MA1 lo6hi register data readout FreqReg via FREQ(7:5) selected in accordance with table on page 17 tpL = max(|tpLine - tpLx|); x= 1 ... n FreqSens via FREQ(4:0) selected in accordance with table on page 17 8 8 8 8 8 0 2 50 50 indefinite 25 % TMAS 320 1/f(CLK) % TMAS % TMAS Max. Unit l65 l65 l66 l67 l68 l69 l70 Ttos TMAR tMA0h tMA1h tMAth tsSL thSL 8 9 9 9 9 9 9 55 2 25 75 50 30 20 256 % TMAS TMAS % TMAR % TMAR % TMAR ns ns Register Mode* l71 Ttor Permissible Timeout (Slave) 9 80 % TMAR *) For clocking to occur in register mode the slaves must have signaled that they are ready for register mode communication (see page 17). Figure 8: Timing diagram of sensor mode Figure 9: Timing diagram of register mode Evaluating SL1 Signals In BiSS mode delay times of longer than one clock cycle are permissible, with the result that line delays during communication are negligible. Evaluation of the sensor response is delayed until the first falling edge at SL1 while at MA1 the clock signal continues to be output. Within one MA1 clock cycle four equally distributed sampling instances are available. Following the falling edge at SL1, the slave's acknowledge signal, the SL1 level is evaluated two sampling instances on, close to the center of the transmitted bit. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 11/26 OPERATING REQUIREMENTS: BiSS Interface (SSI mode) Operating conditions: Register bit SELSSI = 1; VDD = 3 ... 5.5 V, Ta = -25 ... 85 C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD Item l80 l81 l82 l83 l83 Symbol TMAS tMASh tMASl tsDC thDC Parameter Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Setup Time: SL1 stable before MA1 lo6hi Hold Time: SL1 stable before MA1 lo6hi Conditions FreqSens uber FREQ(4:0) selected in accordance with table on page 17 Fig. Min. 10 10 10 10 10 30 10 2 50 50 Max. 320 1/f(CLK) %TMAS %TMAS ns ns Unit Figure 10: Timing diagram of SSI mode. Evaluating SL1 Signals In BiSS interface SSI mode SL1 values are sampled with the rising edge at MA1. An overall delay of the sensor response to the clock at MA1, caused by process times in the sensor or transmission times, is permissible up to the length of one clock cycle. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 12/26 DESCRIPTION OF FUNCTIONS iC-MB3 must be configured in accordance with the sensors connected to it; to this end a special area of memory has been included in the device. The other memory banks are used for the interim storage of incoming slave data or of slave data yet to be transmitted. iC-MB3's second main component is its logic blocks which enable communication with the controller and generate the BiSS interface protocol on the slave side of the chip. Microcontroller Interface Via pins CFGSPI and INT_NMOT iC-MB3 can be configured for operation with an SPI-competent microcontroller, an Intel 8051 controller or a 68HC11 Motorola controller. Here, 8-bit multiplex mode is used, in which the bidirectional data bus alternately transmits addresses and data in blocks of 8 bits (see Figures 3 to 6). Communication Modes CFGSPI 0 0 1 INT_NMOT 0 1 Mode Motorola 68HC11 Intel 8051 SPI (polarity= 0, phase= 0) Figure 11: Wiring diagram for the microcontroller and iC- MB3. When operated in conjunction with an SPI controller pin ALE is used as a clock input (SCK) and pin NCS as an enable input (NCS), with DB0 as the data input (SI) and DB1 as the data output (SO). Data is transmitted serially in successive blocks of 8 bits (command, address and data). Four commands are available. These are WriteData (0000 0010b), ReadData (0000 0011b), ReadStatus (0000 0101b) and WriteInstruction (0000 0111b). The first two commands can be used to write data to or read data from iC-MB3's registers. The latter two commands are truncated write and read commands where the start address is fixed (namely that of the command register to address 244 and that of the status register to address 240). This means that it is not necessary to give an address, with the data directly adhering to the command. With all commands it is possible to transmit several bytes of data consecutively if the NCS signal is not reset and ALE/SCK continues to be clocked. The address transmitted (240 for ReadStatus and 244 for WriteInstruction) is then the start address which is internally increased by 1 following each transmitted byte. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 13/26 Figure 12: SPI transmission protocol (polarity 0, phase 0) iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 14/26 BiSS(SSI) Interface Configurations Device Registers Address1) 00 ... 63 Description Sensor Data - 64 bits per Slave Slave 1 Slave 2 Slave 3 Addresses 07...00; Addresses 15...08; Addresses 23...16; lowest byte in Adr. 00 lowest byte in Adr. 08 lowest byte in Adr. 16 reserved 159 ... 128: Register Data (32 bytes) 191 ... 160: reserved for additional register data Slave Configuration Data - 32 bits per Slave Slave 1 Slave 2 Slave 3 Addresses 195...192 Addresses 199...196 Addresses 203...200 Configuration of Register Communication Configuration of Master Status information and command register Dir.2) in/out Adr. 63...24 reserved for slaves 4...8 bidir in Adr. 223...204 reserved for slaves 4...8 in in in/out 64 ... 127 128 ... 191 192 ... 223 224 ... 229 230 ... 239 240 ... 255 1) 2) All addresses are decimals unless otherwise stated. Direction in: Can only be written to by the C out: Can be read out only by the C in/out: Sections can be written to by the C in part and only be read out in part bidir: Can be written to and read out by the C Reserved address range for other master devices. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 15/26 Sensor Data, Multicycle Data and Slave Configuration SL1 07 ... 00 Address Description SL2 SL3 15 23 ... ... Sensor Data - SDATA(63...0) 08 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Configuration Sensor Data 192 196 200 ACTnSENS ENSENS SDLEN(5:0) Sensor CRC 193 197 201 INVCRCS SENSCRCPOLY(7:1) 194 198 202 Data Conversion 0x00, GRAY= 0: no conversion, for incoming data in binary format 195 199 203 reserved 0x00 Bit 1 Bit 0 0x80, GRAY= 1: Gray-to-binary conversion, for incoming data in Gray code Key to the configuration bits: S S S S S S 1) 2) ACTnSENS ENSENS: SDLEN: INVCRCS: SENSCRCPOLY: GRAY Access to slave data: Read (0), Write (1) Adaptation to slave sensor data: available (1), not available (0) Bit length of sensor data 1) Transmission of CRC bits for sensor data: inverted (1), not inverted (0) CRC polynomial for verification of sensor data 2) Gray/binary data conversion of sensor (required for SSI encoders) The length of the data should be given minus 1, i.e. for 64 data bits enter 63. If 0000 0000b is entered as the CRC polynomial, no cyclic redundancy check is carried out. As the last bit of a CRC polynomial is always 1 this is not entered in the polynomial register but added in the master. A CRC polynomial of up to 8 bits is thus possible. Should the full polynomial length not be required, the polynomial (minus its final 1) must be justified right and the spaces before it filled with zeros. For example, CRC polynomial 10 0011b is stored as 001 0001b. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 16/26 Configuration Register Communication Address Description 224 225 226 227 228 229 Not used Not used Start Address Count Of Bytes Channel Select SlaveID REGVERS Bit 7 WNR - Bit 6 - Bit 5 REGNUM(5) Bit 4 - Bit 3 REGADR(6:0) Bit 2 REGNUM(4:0) Bit 1 - Bit 0 - CHSEL(8:1) SLAVEID(2:0) - Configuration Master Address Description 230 231 232 233 Frequency Division Not used Frequency Division AutoGetsens Not used - Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - Bit 2 - Bit 1 - Bit 0 - FREQ(7:0) FREQAGS(7:0) - Device ID 234 235 Revision Type 0 0 0 0 0 0 1 0 1000 0011b Configuration Channel 236 237 238 239 Slave Location Mode of Operation Mode of Operation Not used SELSSI4 SELSSI8 BiSSMOD4 BiSSMOD8 SELSSI3 SELSSI7 - SLAVELOC(8:1) BiSSMOD3 BiSSMOD7 SELSSI2 SELSSI6 BiSSMOD2 BiSSMOD6 SELSSI1 SELSSI5 BiSSMOD1 BiSSMOD5 - Key to the configuration bits: S SELSSI: S BiSSMOD: Type of protocol: BiSS (0), SSI (1) BiSS protocol model: BiSS model A or B (0), BiSS-A/S (1) Status Information and Command Register Address Description 240 241 242 243 244 245 246 247 248 249 250...255 1) 2) 3) 4) d Bit 7 nERR SVALID4 SVALID8 CDM TIMEOUT BREAK MAv0 REG4 REG8 - Bit 6 nWDERR d d REG 2, 4) UCREADSENS MAf0 SL4 SL8 - Bit 5 d SVALID3 SVALID7 REGBYTES(5) SWRAMBANK MAvS REG3 REG7 - Bit 4 nSENSERR d d Bit 3 nREGERR SVALID2 SVALID6 Bit 2 REGEND d d REGBYTES(4:0) Bit 1 d SVALID1 SVALID5 Bit 0 EOT d d Status Information Validity Messages 1,2) Validity Messages 1,2) Register Messages Command Register Control Flages Not used Not used Channel Status Channel Status Not used INIT MAfS SL3 SL7 - REGCMD reserved REG2 REG6 - GETSENS0 IDDQ 3) SL2 SL6 - GETSENS1 IFTEST 3) REG1 REG5 - AGS CLKENI SL1 SL5 - Reserved addresses for master devices featuring a higher slave or channel count, or more memory for register data. Any attempt to write to this register sets register values to 0. Two memory banks available. iC-Haus device test only, set to 0. For iC-MB3 the register bit REG is equal to REG1. Bit not relevant (don't care). iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 17/26 Configuration - Master Master Clock The master clock, either generated by the basic clock of the internal 20 MHz oscillator (CLKENI = 1) or by an external clock oscillator (CLKENI = 0) which supplies pin CLK, is set with the aid of the frequency division register (address 230). The clock frequency for both BiSS sensor and SSI modes is set via FREQ(4:0) in accordance with the table on the top right. With an external clock pulse of fCLK = 20 MHz clock frequencies ranging from 62.5 kHz to 10 MHz can thus be selected for sensor data transmission. Both BiSS and SSI devices recognize an idle bus at the end of a transmission cycle via a monoflop timeout elapsing (timeoutSENS, see BiSS protocol). The choice of possible clock frequency is thus limited as the duration of both the high and low level may not exceed the shortest timeout of all of the connected subscribers (slaves). BiSS devices switch to register mode on recognizing that the bus is idle after a high-low transition at the clock input and signal this state back to the master on the data line. The clock frequency in BiSS register mode is set via FREQ(7:5) and can lie within a range of ca. 244 Hz to 5 MHz. Here selection is also limited as with the above; a different monoflop timeout now recognizes the idle bus at the end of the cycle (timeoutREG, see BiSS protocol). Additionally, BiSS devices generally only permit a lower clock frequency (such as 250 kHz maximum, for example) because the clock form has to be evaluated as a PWM signal. Master Clock for BiSS Sensor Mode and SSI (FreqSens) FREQ(3:0) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQ(4) = 0 fCLK/2 fCLK/4 fCLK/6 fCLK/8 fCLK/10 fCLK/12 fCLK14 fCLK/16 fCLK/18 fCLK/20 fCLK/22 fCLK/24 fCLK/26 fCLK/28 fCLK/30 fCLK/32 FREQ(4) = 1 not permitted fCLK/40 fCLK/60 fCLK/80 fCLK/100 fCLK/120 fCLK140 fCLK/160 fCLK/180 fCLK/200 fCLK/220 fCLK/240 fCLK/260 fCLK/280 fCLK/300 fCLK/320 A combination of FREQ(4) = 1 and FREQ(3:0) = 0 is not permitted; for a clock frequency of fCLK/20 FREQ(4) = 0 and FREQ(3:0) = 9 must be set. Master Clock for BiSS Register Mode (FreqReg) FREQ(7:5) 0 1 2 3 4 5 6 7 FreqReg FreqSens/2 FreqSens/4 FreqSens/8 FreqSens/16 FreqSens/32 FreqSens/64 FreqSens/128 FreqSens/256 Automatic request for sensor data The frequency with which new requests for sensor data are sent to the slaves is set using FREQAGS according to the table on the right. With an external clock of 20 MHz sensor data request cycles ranging from 1 s to 4 ms are possible. FREQAGS must be set in such a way that the distance between two requests for data is greater than a complete cycle; this consists of the transmission of a request, an acknowledge signal (including any line delays), a start bit (including process times), a register bit (optional), the sensor and CRC bits of each slave and the longest sensor timeout of all the slaves. Automatic Sensor Data Request (FreqAGS) FREQAGS(6:0) 0 1 2 ... 125 126 127 FREQAGS(7)= 0 fCLK/20 fCLK/40 fCLK/60 ... fCLK/2520 fCLK/2540 fCLK/2560 FREQAGS(7)= 1 fCLK/625 fCLK/1250 fCLK/1875 ... fCLK/78750 fCLK/79375 fCLK/80000 iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 18/26 DATA STORAGE - Sensor Data So that new sensor data can be read in during controller accesses iC-MB3 has dual memory banks for sensor data. While sensor data is being read into the first RAM, from the second RAM section the controller can read out the sensor data last read in. The relevant sensor data memory banks are swapped over at the end of the readin procedure; this can be prevented by the controller entering the command register bit UCREADSENS. In parallel with this the validity message register (address 241) and bit REG(address 248) are also swapped. Arrangement of sensor data in the RAM The sensor data memory bank has 8 bytes of memory for each slave which can be interpreted as 64 bits of memory in the array xxxxx111b to xxxxx000b. The sensor data is written to memory area [SDLEN - 1:0] with SDLEN marking the length of the relevant data. Should there be room in the available memory for the CRC bits, these are then also stored with the above data at positions [63:63 - (CRCLEN-1)]. Example Slave 2: 20 bits of sensor data, 6 bits of CRC Adr. 07 ... 00: Adr. 15 ... 08: => total length of 26 bits Adr. 23 ... 16: ... Sensor data Slave 1 Sensor data Slave 2 Adr. 15: SensCRC(5:0), not defined, not defined Adr. 14: - not defined Adr. 13: - not defined Adr. 12: - not defined Adr. 11: - not defined Adr. 10: not defined, not defined, not defined, not defined, SensData(19:16) Adr. 9: SensData(15:8) Adr. 8: SensData(7:0) Sensor data Slave 3 DATA STORAGE - register data For the interim storage of register information read out from or to be written to the slaves iC-MB3 has an individual storage area (addresses 128 to 159) which can temporarily store up to 32 bytes of data. With just one single command this is then transmitted to a slave selected using SLAVEID(2:0) or requested from it as register data. The transmission of register data takes longer than that of sensor data so that the content of the sensor data RAM is then often obsolete. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 19/26 STATUS INFORMATION and COMMAND REGISTER Address 240: Status Messages Bit 7 6 Designation nERR nWDERR Function An error has occurred (low active), equivalent to the pin level at NER (see "Error messaging" on page 22) Watchdog error (low active) on - transmissions triggered by an automatic sensor data request - transmissions of register data 1 Remarks 5 4 3 2 1 0 reserved nSENSERR nREGERR REGEND reserved EOT End of transmission: signals the end of sensor or register data transmission before timed out CRC error in the sensor data (low active) CRC error during the transmission of register data (low active) End of register data transmission 4 2 3 4 1. A watchdog error is triggered during the automatic transmission of sensor data if no new cycle could be initiated; bit AGS in the command register is reset and the automatic request for sensor data aborted. During the transmission of register data a watchdog error is triggered if the slave shows no response, i.e. if it does not answer the first falling master edge with a low or fails to generate a start bit. 2. If a sensor data error is signaled the faulty sensor can be verified by reading out address 241 (validity message). 3. If a register data error is generated the number of bytes transmitted correctly before the error occurred can be determined by reading out the register message REGBYTES (address 243, bits 5...0). In the event of error the transmission of data is terminated. 4. Bit is not relevant (don't care). Address 241: Validity Messages Bit 7 6 5 4 3 2 1 0 Designation reserved SVALID4 reserved SVALID3 reserved SVALID2 reserved SVALID1 Function Not used Not used Not used Readout sensor data from slave 3 valid Not used Readout sensor data from slave 2 valid Not used Readout sensor data from slave 1 valid Remarks 1 1 1 1 1 1 1 1 1. Any attempt to write to this register resets the validity messages. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 20/26 Address 243: Register Messages Bit 7 6 5 4...0 Designation CDM TIMEOUT REG REGBYTES(5) Function Control data timeout elapsed (1), not elapsed (0) Current register data bit at the slave operating on BiSS model C Not used 3 Remarks 1 2 REGBYTES(4:0) Number of register bytes transmitted correctly if an error occurs 1. A new control data communication can only be made once the CDM timeout has elapsed; a new CDM data frame may not be introduced before this time. 2. During the data transmission in BiSS C-Mode protocol, where register data is transmitted together with the sensor data, the current register data bit can be read out via bit REG. Similar to the sensor data this bit also has a second storage section which allows the readout of bits transmitted during the last cycle while a new cycle is running. A swap occurs in parallel with that of the sensor data banks. 3. If no errors occur during transmission these bits are set to 0. Otherwise the number of register bytes successfully transmitted without error is displayed. Address 244: Command Register Bit 7 6 5 4 3 2 1 0 Designation BREAK UCREADSENS SWRAMBANK INIT REGCMD GETSENS0 GETSENS1 AGS Function The current action is aborted (e.g. the clock at MA1 is stopped) RAM bank swapping is blocked All RAM banks and the validity message register are forcibly swapped The sensor is initialized Executes transmissions of register data Single request for sensor data with a high cycle termination (control data bit CDM = 0) Single request for sensor data with a low cycle termination (control data bit CDM = 1) Start of automatic sensor data requests (AutoGetSens) Remarks All bits with the exception of AGS, UCREADSENS and SWRAMBANK are independently deleted by the master once the command has been carried out. All current actions can be aborted using the BREAK command so that a defined state can be resumed if one of the sensors proves faulty, for example. During the readout of more than one sensor data register by the controller it is possible that the RAM banks in the master could be swapped over once a sensor data transmission is complete. So that the controller only reads related values bit UCREADSENS should be set at the start of the readout and returned at the end; this suppresses the RAM swap. With the start of a new sensor data cycle previous values are then overwritten by the new sensor data. Each setting or deletion of bit SWRAMBANK forces the sensor data banks to be swapped over. Data just input, for example, can then be read out if a cycle has ended during UCREADSENS = 1 (this is indicated by EOT in the status register switching to 1 during the suppression of the RAM swap). iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 21/26 The sensor chain can be initiated using the command INIT. A set REG bit starts the transmission of register data between iC-MB3 and a sensor. The transmission of sensor data can be triggered via bits GETSENS0 and GETSENS1. In both instances a new transmission process is initiated; the difference between the two commands lies in how the transmission cycle is ended. With GETSENS0 the cycle finishes with a high; GETSENS1 ends on a low. When initializing the sensor data transmission via GETSENS0 = 1 and GETSENS1 = 1, the cycle finishes with a level determined by the REG bit entered (Address 243, bit 6), i.e. for REG = 0 with a high or for REG = 1 with a low. By this function register data can be transmitted to slaves operating on the BiSS protocol model C principle in parallel to the transmission of sensor data (see "Transmission of register data in sensor mode"). If an AGS bit has been set sensor data is read in cyclically according to the cycle frequency set in register 232 (FREQAGS) without any further commands being issued by the controller. Registers start address (REGADR, address 226), number of bytes (REGNUM, address 227) and slave ID (SLAVEID, address 229) stipulate from which slave register address onwards how many bytes are to be written to or read out from which specific slave. A byte count of 0 entered for REGNUM signals the transmission of a single register value; a 31 indicates the transmission of 32 register values. In the register REGBYTES (address 243) a 0 is entered if communication has proved error free. In the event of error the number of registers correctly read or written is displayed. iC-MB3 does not support autonomous register communication as with BiSS C.Mode protocol, thus it is imperative that address 229's bit REGVERS remain set to 0. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 22/26 Initialization (for slaves with BiSS B-Mode register communication) To initialize the bus subscribers and to allow them to find their position in the queue (and particularly so that the first slave recognizes its position as such) the master line must be set to 0 after a 1 period (longer than the longest sensor timeout). The slaves themselves signal that initialization has been successful with a 0 on line SL1. During initialization internal counters and error flags in the master are deleted or set as appropriate. Should a slave prove faulty and not switch to 0 initialization must be aborted by a BREAK command. Initialization ends when the CDM timeout flag is set (address 243). Communication in sensor mode The transmission of sensor data begins when at pin MA1 the master outputs the clock signal with the clock frequency selected by FREQ. The line delay, i.e. the transmission propagation until an acknowledgement is generated at SL1, is determined from the second falling edge onwards. While the clock continues to be output at MA1 the master waits for the slaves' start bit (1) signaling the start of data transmission. Following this the actual clocking out of sensor data begins, i.e. the sensors place a new bit on the SL1 line with each rising edge on the MA1 line. The sensor data being input into the master and the ensuing sets of CRC data are written to the appropriate sensor data RAM. At the same time the new CRC value is calculated in accordance with InvSensCRC and using the CRC polynomial stored in the configuration RAM. Should, after entry of the last CRC bit, the system ascertain that transmission was faulty the relevant validity message in address 241 is deleted and error message nSENSERR set in the status register at address 240. At the same time the sensor data RAM banks are swapped. Register communication in BiSS B-Mode Once the slaves have signaled their readiness for register communication (SL1 = 0) the addressing sequence is compiled, consisting of a start bit (1), the slave ID, the register address, the write/read flag, the inverted CRC calculated from this and a stop bit (0). This sequence is then transmitted bit by bit. At the same time the ID distribution among the slaves is checked; should none of the slaves react (should SL1 not signal a 1 after 9 clock pulses) communication is aborted and a register error message generated (nREGERR = 0). The same happens if the slave response is not 0 after the 17th rising edge at MA1. If a register value is to be transmitted to a slave transmission of the new register value begins after 17 clock pulses (i.e. following the transmission of the start bit, slave ID, register address, WNR, CRC and stop bit). This new register value consists of a start bit (1), the new contents of the register, the inverted CRC code and a stop bit (0). At the same time the slave response (SL1) is checked. If the slave does not send a start bit for any reason (if the register addressed does not exist, for example, or access to a write protected register is attempted) communication is aborted after 4,096 MA1 clock pulses and the message nWDERR generated; a register error (nREGERR = 0) is signaled if the CRC proves faulty. If transmission has proved free of error further register values are then compiled as needed and transmitted until communication with the register has ended. If no errors have occurred during communication register 243 then has a value of 0; in the event of error this value is the number of bytes transmitted correctly. When reading out a register value from a slave, following a correct addressing sequence (see above) the system waits while the clock pulse continues to be output at MA1 until the addressed slave sends a start bit. During this waiting period a slave can read out a connected EEPROM, for example, and then transmit this value to the master. Once the slave's start bit has been entered into the master the actual data bits are stored and the CRC carried out on the fly. This cyclic redundancy check operates with the fixed polynomial 10011b and with inverted CRC bits. Should a CRC error occur during transmission this is signaled by a register error; the number of register values transmitted without error is stored in register 243 and further communication aborted. If no errors occur during the transmission of data the next register values can be transmitted from the slave to the master by continued clock pulses at MA1. Register 243 contains a 0 if transmission has proved error free. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 23/26 At the end of communication in register mode the CDM timeout flag is set (address 243). Error messaging In sensor mode the validity of data is stored separately for each slave in the validity message register (address 241). In the event of error the appropriate validity message is deleted and nSENSERR set to 0 in the status register. The error is signaled at pin NER. In register mode a register error (nREGERR = 0) or a slave start signal missed for at least 4,096 MA1 clock pulses results in an error message at NER. As following initialization no valid sensor data yet exists all the bits in the validity message (address 241) are deleted; no display is generated at pin NER, however. A watchdog error is triggered if during the automatic sensor data requests no new readout cycle was able to be initiated. In this instance bit AGS is reset in the command register and the cyclic sensor data requests aborted. A watchdog error is also triggered if a slave response is lacking during the transmission of register data. This has two possible causes; either a slave does not respond to the first falling edge with a low or the slave fails to generate a start bit. It is possible to connect other components to pin NER which can also generate an error message; this can then be read out via bit nERR in the status register at address 240. Register communication in sensor mode (BiSS C-Mode) In the BiSS C-Mode protocol it is possible to send register data to or receive register data from a slave during the cyclic sensor data transmission. In conjunction with iC-MB3 the microcontroller must take care of control data communications, and has to employ GETSENS0 and GETSENS1 to transmit the required CDM data. For register data transmission in the opposite direction, from a sensor to the BiSS master, an additional bit is introduced and filled in by the responding slave before the sensor data. So that the first data bit received is treated as CDS, BiSSMOD1 must be set to 1 (address 237). iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 24/26 APPLICATION HINTS Example system: iC-MB3 with two interpolators iC-NQ Figure 13: Example configuration Figure 14: Example BiSS device description file in XML Assumptions: Sensor 1: iC-NQ with angle resolution 8,192: 13 bit angle data, 2 error bits, CRC polynomial 10 0101b and inverted output, TimeoutSENS: 2,62 s iC-NQ with angle resolution 1,024 and period counting: 8 bit period counter data plus 10 bit angle data, 2 error bits, CRC polynomial 10 0101b and an inverted output; TimeoutSENS: 2,62 s 20 MHz (according to the electrical characteristics in the data sheet) => FREQ(4:0) = 00000b (10 MHz) => FREQ(7:5) = 101b (156 kHz) Sensor 2: iC-MB3 clock: Setting the master clock for sensor mode: max. 10 MHz Setting the master clock for register mode: max. 250 kHz Setting the cycle time for the automatic sensor data request: without transmission delays and processing times => cycle time = (3+ (15+6+1) + (20+6+1) ) clock pulses +TimeoutSENS = 52*0,1s + 2,62s = 7,82s .156 * tCLK AutoGetSens time > cycle time => FREQAGS $ 7 iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 25/26 Example system: Required configurations of iC-MB3 Configuration Master Address Description 230 232 Frequency Division Frequency Division AutoGetsens Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1010 0000b 0000 0111b Bit 2 Bit 1 Bit 0 Slave Configuration: Slave 1 Address 192 193 194 195 Description Sensor data Sensor-CRC Data Conversion reserved Bit 7 0 1 0x00 0x00 Bit 6 1 Bit 5 Bit 4 Bit 3 00 1110b 001 0010b Bit 2 Bit 1 Bit 0 Slave Configuration: Slave 2 Address 196 197 198 199 Description Sensor data Sensor-CRC Data Conversion reserved Bit 7 0 1 0x00 0x00 Bit 6 1 Bit 5 Bit 4 Bit 3 01 0011b 001 0010b Bit 2 Bit 1 Bit 0 Slave Configuration: Slave 3 Address 200 201 202 203 Description Sensor data Sensor-CRC Data Conversion reserved Bit 7 0 0x00 0x00 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not relevant not relevant This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying -- even as an excerpt -- is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. iC-MB3 BiSS INTERFACE MASTER, 1-Chan./3-Slaves Rev D1, Page 26/26 ORDERING INFORMATION Type iC-MB3 Demo Board SPI Demo Board PAR Package TSSOP24 4.4 mm Order designation iC-MB3 TSSOP24 iC-MB3 EVAL MB3D-S iC-MB3 EVAL MB3D-P BiSS PC-LPT Adapter BiSS PC-USB Adapter Please refer to descriptions available separately. For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel +49-6135-9292-0 Fax +49-6135-9292-192 http://www.ichaus.com E-mail sales@ichaus.com Appointed local distributors: http://www.ichaus.de/support_distributors.php |
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